View IBM0418A41BLAB_38923.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

.
www..com
Preliminary
Features
IBM0418A81BLAB IBM0436A81BLAB IBM0418A41BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
* 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations * 0.25 Micron CMOS technology * Synchronous Pipeline Mode of Operation with Self-Timed Late Write * Single Differential HSTL Clock * +2.5V Power Supply, Ground, 1.5, 1.8V VDDQ, and 0.90V VREF * HSTL Input and Output levels * Registered Addresses, Write Enables, Synchronous Select, and Data Ins
* Registered Outputs * Common I/O * Asynchronous Output Enable * Synchronous Power Down Input * Boundary Scan using limited set of JTAG 1149.1 functions * Byte Write Capability and Global Write Enable * 7 x 17 Bump Ball Grid Array Package with SRAM JEDEC Standard Pinout and Boundary SCAN Order
Description
The 4Mb and 8Mb SRAMs--IBM0436A41BLAB, IBM0418A41BLAB, IBM0418A81BLAB, and IBM0436A81BLAB--are Synchronous Pipeline Mode, high-performance CMOS Static Random Access Memories that are versatile, wide I/O, and can achieve 3ns cycle times. Differential K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of the K clock, all Addresses, Write-Enables, Sync Select, and Data Ins are registered internally. Data Outs are updated from output registers off the next rising edge of the K clock. An internal Write buffer allows write data to follow one cycle after addresses and controls. The device is operated with a single +2.5V power supply and is compatible with HSTL I/O interfaces.
crrh2519.07 12/13/00
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
Page 1 of 25
www..com IBM0418A41BLAB
IBM0418A81BLAB
IBM0436A81BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
x36 BGA Pinout (Top View)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQ23 DQ20 VDDQ DQ18 DQ25 VDDQ DQ34 DQ32 VDDQ DQ29 DQ27 NC NC VDDQ 2 SA NC SA DQ19 DQ26 DQ22 DQ24 DQ21 VDD DQ35 DQ33 DQ31 DQ30 DQ28 SA NC TMS 3 SA SA SA VSS VSS VSS SBWc VSS VREF VSS SBWd VSS VSS VSS M1* SA TDI 4 NC NC VDD ZQ SS G NC NC VDD K K SW SA0 SA1 VDD SA TCK 5 SA SA SA VSS VSS VSS SBWb VSS VREF VSS SBWa VSS VSS VSS M2* SA TDO 6 SA NC, SA(8Mb) SA DQ10 DQ12 DQ13 DQ15 DQ17 VDD DQ8 DQ6 DQ4 DQ3 DQ1 SA NC NC 7 VDDQ NC NC DQb9 DQb11 VDDQ DQb14 DQb16 VDDQ DQ7 DQ5 VDDQ DQ2 DQ0 NC ZZ VDDQ
Note: * M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VSS and VDD, respectively.
x18 BGA Pinout (Top View)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQ9 NC VDDQ NC DQ12 VDDQ NC DQ13 VDDQ DQ14 NC NC NC VDDQ 2 SA NC SA NC DQ15 NC DQ16 NC VDD DQ11 NC DQ17 NC DQ10 SA SA TMS 3 SA SA SA VSS VSS VSS SBWb VSS VREF VSS NC VSS VSS VSS M1 SA TDI 4 NC NC VDD ZQ SS G NC NC VDD K K SW SA0 SA1 VDD NC TCK 5 SA SA SA VSS VSS VSS NC VSS VREF VSS SBWa VSS VSS VSS M2 SA TDO 6 SA NC, SA(8Mb) SA DQ1 NC DQ5 NC DQ2 VDD NC DQ7 NC DQ0 NC SA SA NC 7 VDDQ NC NC NC DQ4 VDDQ DQ8 NC VDDQ DQ3 NC VDDQ NC DQ6 NC ZZ VDDQ
Note: * M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VSS and VDD respectively.
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
crrh2519.07 12/13/00
Page 2 of 25
www..com
Preliminary
IBM0418A81BLAB IBM0436A81BLAB IBM0418A41BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Pin Description
Address Input SA0-SA18 for 512K x 18 SA0-SA17 for 256K x 36 SA0-SA17 for 256K x 18 SA0-SA16 for 128K x 36 Data I/O DQ0-DQ17 for 512K x 18 DQ0-DQ35 for 256K x 36 Differential Input Register Clocks Write Enable, Global Write Enable, Byte a (DQ0-DQ8) Write Enable, Byte b (DQ9-DQ17) Write Enable, Byte c (DQ18-DQ26) Write Enable, Byte d (DQ27-DQ35) IEEE 1149.1 Test Inputs (LVTTL levels) IEEE 1149.1 Test Output (LVTTL level)
SA0-SA18
G
Asynchronous Output Enable
DQ0-DQ35
SS
Synchronous Select
K, K SW SBWa SBWb SBWc SBWd TMS,TDI,TCK TDO
M1, M2 VREF(2) VDD VSS VDDQ ZZ ZQ NC
Clock Mode Inputs - Selects Single or Dual Clock Operation. HSTL Input Reference Voltage Power Supply (+2.5V) Ground Output Power Supply Synchronous Sleep Mode Output Driver Impedance Control No Connect
Ordering Information (These are all possible sorts; some may not be qualified.)
Part Number IBM0418A41BLAB - 3 IBM0418A41BLAB - 3F IBM0418A41BLAB - 3N IBM0418A41BLAB - 4 IBM0418A41BLAB - 5 IBM0436A41BLAB - 3 IBM0436A41BLAB - 3F IBM0436A41BLAB - 3N IBM0436A41BLAB - 4 IBM0436A41BLAB - 5 IBM0418A81BLAB - 3 IBM0418A81BLAB - 3F IBM0418A81BLAB - 3N IBM0418A81BLAB - 4 IBM0418A81BLAB - 5 IBM0436A81BLAB -3 IBM0436A81BLAB -3F IBM0436A81BLAB - 3N IBM0436A81BLAB -4 IBM0436A81BLAB -5 Organization 256K x 18 256K x 18 256K x 18 256K x 18 256K x 18 128K x 36 128K x 36 128K x 36 128K x 36 128K x 36 512K x 18 512K x 18 512K x 18 512K x 18 512K x 18 256K x 36 256K x 36 256K x 36 256K x 36 256K x 36 Speed 1.7ns Access / 3.0ns Cycle 1.8ns Access / 3.3ns Cycle 1.8ns Access / 3.7ns Cycle 2.0ns Access / 4.0ns Cycle 2.25ns Access /5.0ns Cycle 1.7ns Access / 3.0ns Cycle 2.0ns Access / 3.3ns Cycle 1.8ns Access / 3.7ns Cycle 2.0ns Access / 4.0ns Cycle 2.25ns Access /5.0ns Cycle 1.7ns Access / 3.0ns Cycle 1.8ns Access / 3.3ns Cycle 1.8ns Access / 3.7ns Cycle 2.0ns Access / 4.0ns Cycle 2.25ns Access /5.0ns Cycle 1.7ns Access / 3.0ns Cycle 1.8ns Access / 3.3ns Cycle 1.8ns Access / 3.7ns Cycle 2.0ns Access / 4.0ns Cycle 2.25ns Access /5.0ns Cycle Leads 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA
crrh2519.07 12/13/00
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
Page 3 of 25
www..com IBM0418A41BLAB
IBM0436A81BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
IBM0418A81BLAB
Preliminary
Block Diagram
SBW REG
SBW
READ ADD REG
WRITE0 ADD REG
WRITE1 ADD REG
SBW0 REG
Row Decode
SA0-SA18
DOC_MUX0 2:1 MUX
DOC_Array0
READ
K
Col Decode Read/Wr Amp WRITE
LATCH
MATCH1
MATCH
SS
WR_BUF1
ZZ
SW
LATCH0 DOC_MUX2 2:1 MUX SW0 REG SW1 REG DOC_MUX1 2:1 MUX
SS0 REG
SS1 REG
DOC_ DOUT0
G
DQ0-DQ35
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
crrh2519.07 12/13/00
Page 4 of 25
WR_BUF0
www..com
Preliminary
IBM0418A81BLAB IBM0436A81BLAB IBM0418A41BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
SRAM Features
Late Write Late Write function allows for write data to be registered one cycle after addresses and controls. This feature eliminates one bus-turnaround cycle, necessary when going from a Read to a Write operation. Late Write is accomplished by buffering write addresses and data so that the write operation occurs during the next write cycle. When a read cycle occurs after a write cycle, the address and write data information are stored temporarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array will be updated with address and data from the holding registers. Read cycle addresses are monitored to determine if read data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array occurs on a byte-by-byte basis. When only one byte is written during a write cycle, read data from the last written address will have new byte data from the write buffer and remaining bytes from the SRAM array. Mode Control Mode control pins M1 and M2 are used to select four different JEDEC-standard read protocols. This SRAM supports Single Clock, Pipeline (M1 = VSS, M2 = VDD). This datasheet only describes Single Clock Pipeline functionality. Mode control inputs must be set with power up and must not change during SRAM operation. This SRAM is tested only in the Pipeline mode. Sleep Mode Sleep Mode is enabled by switching synchronous signal ZZ High. When the SRAM is in Sleep mode, the outputs will go to a High-Z state and the SRAM will draw standby current. SRAM data will be preserved and a recovery time (tZZR) is required before the SRAM resumes normal operation. RQ Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow for the SRAM to adjust its output driver impedance. The value of RQ must be tbdX the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching is between 175 and 350, with the tolerance described in Programmable Impedance Output Driver DC Electrical Characteristics on page 9. The RQ resistor should be placed less than two inches away from the ZQ ball on the SRAM module. The total external capacitance (including wiring ) seen by the ZQ ball should be minimized (less than 7.5 pF). Programmable Impedance and Power-Up Requirements Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. One evaluation occurs every 64 clock cycles and each evaluation may move the output driver impedance level only one step at a time towards the optimum level. The output driver has 32 discrete binary weighted steps. The impedance update of the output driver occurs when the SRAM is in High-Z. Write and Deselect operations will synchronously switch the SRAM into and out of HighZ, therefore triggering an update. The user may choose to invoke asynchronous G updates by providing a G setup and hold about the K clock to guarantee the proper update. There are no power-up requirements for the SRAM; however, to guarantee optimum output driver impedance after power up, the SRAM needs 4096 clock cycles followed by a Low-Z to High-Z transition. Power-Up and Power-Down Sequencing The Power supplies need to be powered up in the following order: VDD, VDDQ, VREF, and Inputs. The powerdown sequencing must be the reverse. VDDQ can be allowed to exceed VDD by no more than 0.6V.
crrh2519.07 12/13/00
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
Page 5 of 25
www..com IBM0418A41BLAB
IBM0436A81BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
IBM0418A81BLAB
Preliminary
Clock Truth Table
K LH LH LH LH LH LH LH LH X ZZ L L L L L L L L H SS L L L L L L L H X SW H L L L L L L X X SBWa X L H H H L H X X SBWb X H L H H L H X X SBWc X H H L H L H X X SBWd X H H H L L H X X DQ (n) X X X X X X X X High-Z DQ (n+1) DOUT 0-35 DIN 0-8 DIN 9-17 DIN 18-26 DIN 27-35 DIN 0-35 High-Z High-Z High-Z Mode Read Cycle All Bytes Write Cycle 1st Byte Write Cycle 2nd Byte Write Cycle 3rd Byte Write Cycle 4th Byte Write Cycle All Bytes Abort Write Cycle Deselect Cycle Sleep Mode
Output Enable Truth Table
Operation (n, n+1) Read Read Sleep (ZZ = H) Write (SW = L) Deselect (SS = H) G (n) L H X X X DQ (n) DOUT 0-35 High-Z High-Z X X DQ (n+1) DOUT 0-35 High-Z High-Z High-Z High-Z
Absolute Maximum Ratings
Item Power Supply Voltage Output Power Supply Voltage Input Voltage DQ Input Voltage Operating Temperature Junction Temperature Storage Temperature Short Circuit Output Current Symbol VDD VDDQ VIN VDQIN TA TJ TSTG IOUT Rating -0.5 to 2.825 -0.5 to 2.825 -0.5 to 4.3 -0.5 to 2.825 0 to 85 110 -55 to +125 25 Units V V V V C C C mA Notes 1 1 1, 2 1 1 1 1 1
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Excludes DQ inputs.
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
crrh2519.07 12/13/00
Page 6 of 25
www..com
Preliminary
IBM0418A81BLAB IBM0436A81BLAB IBM0418A41BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Recommended DC Operating Conditions (TA = 0 to +85C)
Parameter Supply Voltage Output Driver Supply Voltage Input High Voltage Input Low Voltage Input Reference Voltage Clocks Signal Voltage Differential Clocks Signal Voltage Clocks Common Mode Voltage 1. 2. 3. 4. 5. 6. Symbol VDD VDDQ VIH VIL VREF VIN - CLK VDIF - CLK VCM - CLK Min. 2.5 - 5% 1.4 VREF +0.1 -0.3 0.68 -0.3 0.1 0.55 Typ. 2.5 1.5, 1.8 -- -- 0.90 -- -- -- Max. 2.5 + 5% 1.9 VDDQ + 0.3 VREF - 0.1 0.95 VDDQ + 0.3 VDDQ + 0.6 0.90 Units V V V V V V V V Notes 1 1 1, 2 1, 3 1, 6 1, 4 1, 5 1
All voltages referenced to VSS. All VDD, VDDQ, and VSS pins must be connected. VIH(Max)DC = VDDQ + 0.3 V, VIH(Max)AC = VDDQ + 0.85 V (pulse width 4.0ns). VIL(Min)DC = -0.3 V, VIL(Min)AC = -1.5 V (pulse width 4.0ns). VIN-CLK specifies the maximum allowable DC excursions of each differential clock (K, K). VDIF-CLK specifies the minimum Clock differential voltage required for switching. Peak to Peak AC component superimposed on VREF may not exceed 5% of VREF.
crrh2519.07 12/13/00
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
Page 7 of 25
w w w IBM0418A41BLAB e t 4 U . c o m . D a t a S h e IBM0436A41BLAB
IBM0418A81BLAB
IBM0436A81BLAB Preliminary
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
DC Electrical Characteristics (TA = 0 to +85C, VDD = 2.5V -5%, +5%)
Parameter Symbol IDD3 IDD3F IDD3N IDD4 IDD5 IDD3I IDD3F IDD3N IDD4 IDD5 ISBSS Min. Max. 0.470 0.450 0.435 0.420 0.370 0.450 0.430 0.415 0.400 0.350 150 Units Notes
Average Power Supply Operating Current - x36 (IOUT = 0, VIN = VIH or VIL, ZZ & SS = VIL)
-- --
A
1, 3
Average Power Supply Operating Current - x18 (IOUT = 0, VIN = VIH or VIL, ZZ & SS = VIL)
-- --
A
1, 3
Power Supply Standby Current (SS = VIH, ZZ = VIL. All other inputs = VIH or VIH, IIH = 0) Power Supply Sleep Current (ZZ = VIH, All other inputs = VIH or VIL, IOUT = 0) Input Leakage Current, any input (except JTAG) (VIN = VSS or VDD) Output Leakage Current (VOUT = VSS or VDD, DQ in High-Z) Output "High" Level Voltage (IOH = -8mA) Output "Low" Level Voltage (IOL = +8mA) JTAG Leakage Current (VIN = VSS or VDD) 1. 2. 3.
--
mA
1
ISBZZ
--
100
mA A A V V A
1, 5
ILI
-2
+2
ILO VOH VOL ILIJTAG
-5 VDDQ -.4 VSS -50
+5 VDDQ VSS+.4 +10
2, 4 2, 4 6
IOUT = Chip Output Current. Minimum Impedance Output Driver. The numeric suffix indicates part operating at speed as indicated in AC Characteristics on page 11: i.e., IDD3 indicates 3ns cycle time. 4. JEDEC Standard JESD8-6 Class 1 Compatible. 5. When ZZ = High, spec is guaranteed at 75C junction temperature. 6. For JTAG inputs only.
PBGA Thermal Characteristics
Item Thermal Resistance Junction to Case Symbol RJC Rating 1 Units C/W
Capacitance (TA = 0 to +85C, VDD = 2.5V -5%, +5%, f = 1MHz)
Parameter Input Capacitance Data I/O Capacitance (DQ0-DQ35) Symbol CIN COUT Test Condition VIN = 0V VOUT = 0V Max 4 4 Units pF pF
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
crrh2519.07 12/13/00
Page 8 of 25
www..com
Preliminary
IBM0418A81BLAB IBM0436A81BLAB IBM0418A41BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
AC Input Characteristics
Item AC Input Logic High AC Input Logic Low Clock Input Differential Voltage VREF Peak to Peak ac Voltage Symbol VIH (ac) VIL (ac) VDIF (ac) VREF (ac) 0.7 5% VREF (dc) Min VREF + 0.4 VREF - 0.4 Max Notes 3 3 2 1
1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2. Performance is a function of VIH and VIL levels to clock inputs. 3. See the AC Input Definition figure below.
AC Input Definition
VIH (ac) VREF
VIL (ac)
Programmable Impedance Output Driver DC Electrical Characteristics
(TA = 0 to +85C, VDD = 2.5V -5%, +5%, VDDQ = 1.8 V)
Parameter Output "High" Level Voltage Output "Low" Level Voltage Symbol VOH VOL Min. VDDQ / 2 VSS Max. VDDQ VDDQ / 2 Units V V Notes 1, 3 2, 3
VDDQ RQ 1. IOH = ------------------ -------- + 5 15% @ VOH = VDDQ / 2 For: 175 RQ 350. 5 2 VDDQ RQ 2. IOL = ------------------ -------- 15% @ VOL = VDDQ / 2 For: 175 RQ 350. 2 5
3. Parameter tested with RQ = 250 and VDDQ = 1.8 V.
crrh2519.07 12/13/00
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
Page 9 of 25
www..com IBM0418A41BLAB
IBM0436A81BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
IBM0418A81BLAB
Preliminary
AC Test Conditions T(A = 0 to +85C, VDD = 2.5V -5%, +5%, VDDQ = 1.5, 1.8 V)
Parameter Output Driver Supply Voltage Input High Level Input Low Level Input Reference Voltage Differential Clocks Voltage Clocks Common Mode Voltage Input Rise Time Input Fall Time I/O Signals Reference Level (except K, C Clocks) Clocks Reference Level Output Load Conditions 1. See the AC Test Loading figure below. 2. Parameter tested with RQ = 250 and VDDQ = 1.8 V. Symbol VDDQ VIH VIL VREF VDIF-CLK VCM-CLK TR TF Conditions 1.5, 1.8 1.5 0.3 0.75, 0.90 0.75 0.75, 0.9 0.5 0.5 0.9 Differential Cross Point Units V V V V V V ns ns V V 1, 2 Notes
AC Test Loading
50 50 0.75, 0.9V
25 DQ
5pF 0.9V
50 50 0.75, 0.9V
5pF
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
crrh2519.07 12/13/00
Page 10 of 25
www..com
Preliminary
IBM0418A81BLAB IBM0436A81BLAB IBM0418A41BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
AC Characteristics (TA = 0 to +85C, VDD = 2.5V -5%, +5%)
3 Parameter Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock to Output Valid Address Setup Time Address Hold Time Sync Select Setup Time Sync Select Hold Time Write Enables Setup Time Write Enables Hold Time Data In Setup Time Data In Hold Time Data Out Hold Time Clock High to Output High-Z Clock High to Output Active Output Enable to High-Z Output Enable to Low-Z Output Enable to Output Valid Output Enable Setup Time Output Enable Hold TIme Sleep Mode Setup Time Sleep Mode Hold Time Sleep Mode Recovery TIme Sleep Mode Enable TIme Symbol Min. tKHKH tKHKL tKLKH tKHQV tAVKH tKHAX tSVKH tKHSX tWVKH tKHWX tDVKH tKHDX tKHQX tKHQZ tKHQX4 tGHQZ tGLQX tGLQV tGHKH tKHGX tZVKH tKHZX tZZR tZZE 3.0 1.2 1.2 -- 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 -- 0.5 -- 0.5 -- 0.5 1.5 1.0 1.0 200 -- Max. -- -- -- 1.7 -- -- -- -- -- -- -- -- -- 2.25 -- 2.0 -- 2.0 -- -- -- -- -- 6 0.5 -- 0.5 1.5 1.0 1.0 200 -- Min. 3.3 1.5 1.5 -- 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 -- 0.5 Max. -- -- -- 1.8 -- -- -- -- -- -- -- -- -- 2.25 -- 2.0 -- 2.0 -- -- -- -- -- 6.6 0.5 -- 0.5 1.5 1.0 1.0 200 -- Min. 3.7 1.5 1.5 -- 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 -- 0.5 Max. -- -- -- 1.8 -- -- -- -- -- -- -- -- -- 2.25 -- 2.0 -- 2.0 -- -- -- -- -- 7.4 0.5 -- 0.5 1.5 1.0 1.0 200 -- Min. 4.0 1.5 1.5 -- 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 -- 0.5 Max. -- -- -- 2.0 -- -- -- -- -- -- -- -- -- 2.25 -- 2.0 -- 2.0 -- -- -- -- -- 8 Min. 5.0 1.5 1.5 -- 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 0.5 -- 0.5 -- 0.5 -- 0.5 1.5 1.0 1.0 200 -- Max. -- -- -- 2.25 -- -- -- -- -- -- -- -- -- 2.5 -- 2.5 -- 2.5 -- -- -- -- -- 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 1 3 3 3 3 3 3 3 3 1 1 1 1 1 1 1, 2 1, 2 3F 3N 4 5 Units Notes
1. See the AC Test Loading figure on page 10. 2. Output Driver Impedance update specifications for G induced updates. Write and Deselect cycles will also induce Output Driver updates during High-Z. 3. During normal operation, VIH, VIL, TRISE, and TFALL of inputs must be within 20% of VIH, VIL, TRISE, and TFALL of Clock. 4. For tZZR<200ns, access time will be equal to twice tKHQV.
crrh2519.07 12/13/00
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
Page 11 of 25
www..com IBM0418A41BLAB
IBM0436A81BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
IBM0418A81BLAB
Preliminary
Read and Deselect Cycles Timing Diagram
tKLKH tKHKL K tAVKH tKHKH
SA
A1 tKHAX
A2
A3
A3
A4
tKHSX
SS tSVKH
tWVKH
SW tKHWX tGLQV
G tGHQZ
tKHQX
tKHQZ
DQ
Q1
Q2
Q3
Q4
tGLQX
tKHQV
tKHQX4
tKHQV
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
crrh2519.07 12/13/00
Page 12 of 25
www..com
Preliminary
IBM0418A81BLAB IBM0436A81BLAB IBM0418A41BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Read Write Cycles Timing Diagram
tKLKH tKHKL tKHKH
K tAVKH A1 tSVKH A2 tKHAX A3
SA
A2
A4
SS tKHSX tKHWX SW tWVKH tKHWX SBW tWVKH tWVKH tWVKH tKHWX tKHWX
G tKHQZ tKHDX DQ tKHQV Q1 D2 Q3 Q2 tDVKH tKHDX D4 tKHQV tGHQZ
tDVKH
tKHQX4
Notes: 1. D2 is the input data written in memory location A2. 2. Q2 is output data read from the write buffer, as a result of address A2 being a match from the last write cycle address.
crrh2519.07 12/13/00
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
Page 13 of 25
www..com IBM0418A41BLAB
IBM0436A81BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
IBM0418A81BLAB
Preliminary
Synchronous Sleep Mode Timing Diagram
tKHKH tZVKH K tKHZX ZZ tZZE tKHZX
tZVKH
tZZR DQ tAVKH tKHQV Q1
ADDR
A1
tKHAX Note: for tZZR < 200ns, access time will be equal to 2 x tKHQV.
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
crrh2519.07 12/13/00
Page 14 of 25
www..com
Preliminary
IBM0418A81BLAB IBM0436A81BLAB IBM0418A41BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
IEEE 1149.1 TAP and Boundary Scan
The SRAM provides a limited set of JTAG functions intended to test the interconnection between SRAM I/Os and printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM core. In conformance with IEEE Std. 1149.1, the SRAM contains a TAP controller, Instruction register, Boundary Scan register, Bypass register, and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. Signal List * * * * TCK: TMS: TDI: TDO: Test Clock Test Mode Select Test Data In Test Data Out.
JTAG DC Operating Characteristics (TA = 0 to +85C)
Operates with JEDEC Standard 8-5 (2.5V) logic signal levels
Parameter JTAG Input High Voltage JTAG Input Low Voltage JTAG Output High Level JTAG Output Low Level 1. 2. 3. Symbol VIH1 VIL1 VOH1 VOL1 Min. 1.7 -0.3 2.1 -- Typ. -- -- -- -- Max. VDD+0.3 0.8 -- 0.2 Units V V V V Notes 1 1 1, 2 1, 3
All JTAG inputs and outputs are LVTTL compatible only. IOH1 -|2mA| IOL1 +|2mA|.
JTAG AC Test Conditions (TA = 0 to +85C, VDD = 2.5V -5%, +5%)
Parameter Input Pulse High Level Input Pulse Low Level Input Rise Time Input Fall Time Input and Output Timing Reference Level Symbol VIH1 VIL1 TR1 TF1 Conditions 3.0 0.0 2.0 2.0 1.25 Units V V ns ns V
crrh2519.07 12/13/00
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
Page 15 of 25
www..com IBM0418A41BLAB
IBM0436A81BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
IBM0418A81BLAB
Preliminary
JTAG AC Characteristics (TA = 0 to +85C, VDD = 2.5V -5%, +5%)
Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Setup TMS Hold TDI Setup TDI Hold TCK Low to Valid Data 1. See the AC Test Loading figure on page 10. Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tDVTH tTHDX tTLOV Min. 20 7 7 4 4 4 4 -- Max. -- -- -- -- -- -- -- 7 Units ns ns ns ns ns ns ns ns 1 Notes
JTAG Timing Diagram
tTHTL tTLTH tTHTH
TCK
tTHMX
TMS tMVTH
tTHDX
TDI
tDVTH
TDO
tTLOV
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
crrh2519.07 12/13/00
Page 16 of 25
www..com
Preliminary
IBM0418A81BLAB IBM0436A81BLAB IBM0418A41BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Scan Register Definition
Register Name Instruction Bypass ID Boundary Scan * * The Boundary Scan chain consists of the following bits: * * * * * 36 or 18 bits for Data Inputs, depending on x18 or x36 configuration 18 bits for SA0 - SA14 in x36, 19 bits for SA0 - SA15 in x18 4 bits for SBWa - SBWd in x36, 2 bits for SBWa and SBWb in x18 9 bits for K, K, ZQ, SS, G, SW, ZZ, M1 and M2 3 bits for Place Holders for 8 Mb, 4bits for Place Holders for 4Mb Bit Size x18 3 1 32 51 Bit Size x36 3 1 32 70
* K and K clocks connect to a differential receiver that generates a single-ended clock signal. This signal and its inverted value are used for Boundary Scan sampling.
ID Register Definition
Field Bit Number and Description Part Revision Number (31:28) 0111 0111 0111 0111 Device Density and Configuration (27:18) 011 010 1100 011 100 1011 101 111 0011 101 101 0100 Vendor Definition (17:12) xxxxxx xxxxxx xxxxxx xxxxxx Manufacturer JEDEC Code (11:1) 000 101 001 00 000 101 001 00 000 101 001 00 000 101 001 00 Start Bit(0) 1 1 1 1
128K x 36 256K x 18 512K x 18 256K x 36
crrh2519.07 12/13/00
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
Page 17 of 25
www..com IBM0418A41BLAB
IBM0436A81BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
IBM0418A81BLAB
Preliminary
Instruction Set
Code 000 001 010 011 100 101 110 111 Instruction SAMPLE-Z IDCODE SAMPLE-Z PRIVATE SAMPLE PRIVATE PRIVATE BYPASS 1, 2 5 4 5 5 3 Notes 1, 2
1. Places DQs in High-Z in order to sample all input data regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded TDI when exiting the Shift DR state. 4. SAMPLE instruction does not place DQs in High-Z. 5. This instruction is reserved for the exclusive use of IBM. Invoking this instruction will cause improper SRAM functionality.
List of IEEE 1149.1 Standard Violations * 7.2.1.b, e * 7.7.1.a-f * 10.1.1.b, e * 10.7.1.a-d * 6.1.1.d
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
crrh2519.07 12/13/00
Page 18 of 25
www..com
Preliminary
IBM0418A81BLAB IBM0436A81BLAB IBM0418A41BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Boundary Scan Order (128K x 36), (256K x 36) (PH = Place Holder)
Exit Order 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Signal M2 SA SA SA SA ZZ DQ0 DQ1 DQ2 DQ4 DQ3 DQ5 DQ6 DQ8 DQ7 SBWa K K G SBWb DQ16 DQ17 DQ15 DQ14 Bump # 5R 4P 4T 6R 5T 7T 6P 7P 6N 7N 6M 6L 7L 6K 7K 5L 4L 4K 4F 5G 7H 6H 7G 6G Exit Order 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Signal DQ12 DQ13 DQ11 DQ10 DQ9 SA SA SA SA PH1(4Mb), SA(8Mb) SA SA PH1 SA SA SA SA DQ18 DQ19 DQ20 DQ22 DQ21 DQ23 DQ24 Bump # 6F 7E 6E 7D 6D 6A 6C 5C 5A 6B 5B 3B 2B 3A 3C 2C 2A 2D 1D 2E 1E 2F 2G 1G Exit Order 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal DQ26 DQ25 SBWc ZQ SS PH1 PH2 SW SBWd DQ34 DQ35 DQ33 DQ32 DQ30 DQ29 DQ31 DQ28 DQ27 SA SA SA M1 Bump # 2H 1H 3G 4D 4E 4G 4H 4M 3L 1K 2K 1L 2L 2M 1N 2N 1P 2P 3T 2R 4N 3R
1. Input of PH register connected to VSS. 2. Input of PH register connected to VDD
crrh2519.07 12/13/00
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
Page 19 of 25
www..com IBM0418A41BLAB
IBM0436A81BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
IBM0418A81BLAB
Preliminary
Boundary Scan Order (256K x 18), (512K x 18) (PH = Place Holder)
Exit Order 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Signal M2 SA SA SA SA ZZ DQ5 DQ6 DQ7 DQ8 SBWa K K G DQ4 DQ3 DQ2 DQ1 DQ0 SA SA SA SA PH1(4Mb), SA(8Mb) SA SA Bump # 5R 6T 4P 6R 5T 7T 7P 6N 6L 7K 5L 4L 4K 4F 6H 7G 6F 7E 6D 6A 6C 5C 5A 6B 5B 3B Exit Order 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Signal PH1 SA SA SA SA DQ14 DQ15 DQ16 DQ17 SBWb ZQ SS PH1 PH2 SW DQ13 DQ12 DQ10 DQ11 DQ9 SA SA SA SA M1 Bump # 2B 3A 3C 2C 2A 1D 2E 2G 1H 3G 4D 4E 4G 4H 4M 2K 1L 2M 1N 2P 3T 2R 4N 2T 3R
1. Input of PH register connected to VSS. 2. Input of PH register connected to VDD
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
crrh2519.07 12/13/00
Page 20 of 25
www..com
Preliminary
IBM0418A81BLAB IBM0436A81BLAB IBM0418A41BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
TAP Controller State Machine
1
Test Logic Reset 0 0 Run Test Idle 1 Select DR 0 1 1 Capture DR 0 0 Shift DR 1 1 1 Exit1 DR 0 0 0 0 Pause IR 1 0 Exit1 IR 0 Shift IR 1 1 Select IR 0 Capture IR 0 1
Pause DR 1
Exit2 DR 0 1 1 Update DR 0 1
Exit2 IR 1 Update IR 0
crrh2519.07 12/13/00
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
Page 21 of 25
www..com IBM0418A41BLAB
IBM0436A81BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
IBM0418A81BLAB
Preliminary
7 x17 BGA Dimensions
Top View 22.00 16.764
12.294
12.7 Ref
14.00
Indicates A1 Location
Plate Underfill
Die
0.625 .254
Side View 0.1778 Ref Structural Adhesive Plate Ello' Guv'na! 0.701 0.099 0.71 0.05 Typ Bottom View 0.84 Ref 20.32 Underfill
2.549 0.13
1.27 7.62
1 2 3 4 5 6 7
0.889 0.04 diam. Solder Ball
3.19 Ref ABCDE FGH J K LMNPRTU
Note: All dimensions are in millimeters
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
crrh2519.07 12/13/00
Page 22 of 25
www..com
Preliminary
IBM0418A81BLAB IBM0436A81BLAB IBM0418A41BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
References
The following documents give recommendations, restrictions, and limitations for 2nd level attach process: Double Sided 4Mb SRAM Coupled Cap PBGA Card Assembly Guide Qualification information, including the scope of application conditions qualified, is available from your marketing representative.
Note: This document contains information on products in the sampling and/or initial production phases of development. This information is subject to change without notice. Verify with your IBM field applications engineer that you have the latest version of this document before finalizing a design.
crrh2519.07 12/13/00
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
Page 23 of 25
www..com IBM0418A41BLAB
IBM0436A81BLAB IBM0436A41BLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
IBM0418A81BLAB
Preliminary
Revision Log
Revision 9/98 11/98 Initial release. Updated package diagram. Changed part numbers from Rev A to B. In Programmable Impedance Output Driver DC Electrical Characteristics on page 9: 2/16/99 IOH = (VDDQ / 2) / ((RQ / 5) + 5) 15% @ VOH = VDDQ / 2 For: 175 RQ 350. IOL = (VDDQ / 2) / (RQ / 5) 15% @ VOL = VDDQ / 2 For: 175 RQ 350 7/13/99 Corrected 7 x17 BGA Dimensions. Added 3N speed sort. In DC Electrical Characteristics on page 8: 1/12/2000 ISBSS Changed from 120 mA to 150 mA. ISBZZ Changed from 65 mA to 100 mA Page 14: Timing updated for Synchronous operation. Page 11: 2/09/2000 Sleep Mode Setup time spec added: tZVKH =1.0ns Sleep Mode Hold time spec added: tKHZX =1.0ns Page 22: Enhanced BGA diagram. In AC Characteristics on page 11: tKHQV changed from 1.7 to 1.6ns. Added footnote 5. 12/05/00 tAVKH, tSVKH, tWVKH, tDVKH spec changed from 0.5ns to 0.3ns Added footnote 6. In ID Register Definition on page 17: Revision Number Bits (31:28) defined as 0111. Made various minor editorial changes and format refinements. 12/13/00 Returned AC Characteristics changes made in 12/05/00 document to their previous values. Contents of Modification
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
crrh2519.07 12/13/00
Page 24 of 25
www..com
(R)
pyright and Disclaimer
(c) Copyright International Business Machines Corporation 1998 All Rights Reserved Printed in the United States of America December 2000 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both. IBM IBM Logo Other company, product and service names may be trademarks or service marks of others. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Microelectronics Division 1580 Route 52, Bldg. 504 Hopewell Junction, NY 12533-6351 The IBM home page can be found at http://www.ibm.com The IBM Microelectronics Division home page can be found at http://www.chips.ibm.com crrh2519.07 12/13/00

▲Up To Search▲

Price & Availability of IBM0418A41BLAB

	To Download IBM0418A41BLAB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .